As the density of very large scale integration (VLSI) circuits increases, the testability of those circuits decreases. When testing the design of a VLSI chip, it is possible to trace signals through each circuit module and verify the correct behavior at each step. However, testing for manufacturing defects in this manner would be impractical, as it would require dedicating a large number of pins solely for test purposes at a great cost.
Today, application specific integrated circuits (ASIC) often include millions of gates in a system-on-chip (SoC) configuration with embedded processor cores (often supplied by a third party), memory, and application-specific logic. Testing such circuits is a daunting task, as shown by the quantity of research in design-for-test (DFT) techniques and built-in self-test (BIST) functionality.
One common technique for testing a simple circuit, such as an AND gate, is to apply a series of input vectors and observe the output of the circuit to verify the appropriate behavior. For example, an AND gate includes two inputs, A and B, and an output C. The output C should be the logical AND of the inputs A and B. A series of test vectors, [(A1,B1),C1], [(A2,B2),C2], . . . [(An,Bn),Cn], may be used to verify the operation of the AND gate. For example, the first vector may be [(0,0),0], i.e., a “0” is applied to each of A and B, and the expected output is “0”. Similarly, for the test vector [(1,1),1], a “1” is applied to each of A and B and the expected output of the AND gate is “1.” If the expected output is not observed, then the circuit is defective. As circuit complexity increases, the same basic technique can be applied by making components of the circuit observable and controllable so that the inputs to a circuit or a component of a complex integrated circuit may be controlled and the corresponding output observed.
One technique used to make integrated circuits both controllable and observable is to incorporate scan registers into the circuit design. For example, Huffman illustrated that sequential logic circuits may be modeled as combinatorial logic in conjunction with a register (e.g., latch, flip-flop) to store state. The register includes an input from the combinatorial logic so that the state may be changed, an output to the combinatorial logic so that the state may be used by the logic, and a clock signal. The register may be modified to a scan register to implement scan-based DFT. The scan register additionally includes a mode signal to switch the scan register between a normal mode and a test mode; an input signal to receive a test vector to be used by the combinational logic circuit; and an output signal so that test results may be observed.
To reduce the number of pins needed in an integrated circuit employing scan-based DFT, a series of scan registers may be connected in a chain such that scan inputs and outputs may be serially shifted through the chain to reduce the number of pins needed to fully test the integrated circuit.